74138 3-to-8 line Decoder/Demultiplexer IC PDIP-16

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The 74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The 74HC138 has 3 binary select inputs.

Technical Specification:

  • Supply Voltage: -0.5 to + 7.0V DC 
  • Input Voltage: -0.5V to VDD + 0.5V
  • Output Voltage: -0.5 to VCC + 0.5V
  • Clamp Diode Current:   ± 20 mA
  • DC Output Current, per pin:± 25 mA
  • DC VCC or GND Current, per pin: ± 50 mA 
  • Storage Temperature Range: -65°C to + 150°C 
  • Power Dissipation: 600 mW
  • O. Package only:  500 mW
  • Lead Temperature (TL) (Soldering 10 seconds): 260°C


  • Designed specifically for high speed
  • Incorporates three enable pins to simplify cascading
  • De-multiplexing capability
  • Schottky clamped for high performance
  • ESD protection
  • Balanced propagation delays
  • Inputs accept voltages higher than VCC


  • Line decoders
  • Servers
  • Digital systems
  • Line De-multiplexing
  • Telecom circuits
  • Memory circuits

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